1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of controlling its output, and more specifically, to a semiconductor memory device in which data of a plurality of bits can be read out simultaneously from its memory cell array and a method of controlling its output.
2. Description of the Background Art
Conventionally, when a semiconductor memory device such as a Dynamic Random Access Memory (hereinafter referred to as a DRAM) is connected to a data transmission bus having a different width, how to control output/input of data to/from the semiconductor memory device is a problem.
FIG. 3 is a block diagram showing a conventional DRAM connected to a data transmission bus having a different bit width. In the figure, the bit width of DRAM 1 is selected to be n bits (n is an integer equal to or larger than 2). In other words, DRAM 1 can write and read data of n bits at a time. Data transmission bus 2 connected to DRAM 1 has its bit width selected to be m bits (m=n/2). An output of n bits from DRAM 1 is divided into an upper bit group BG.sub.U of more significant m bits and a lower bit group BG.sub.L of less significant m bits, and the bit groups are each connected to data transmission bus 2. DRAM 1 is supplied with a row address strobe signal RAS through an input terminal 3, an upper column address strobe signal CAS.sub.U through an input terminal 4, and a lower column address strobe signal CAS.sub.L through an input terminal 5. DRAM 1 is also supplied with address data through input terminals 61-6k.
DRAM 1 shown in FIG. 3 controls output of the upper bit group BG.sub.U in response to the upper column address strobe signal CAS.sub.U and controls output of the lower bit group BG.sub.L in response to the lower column address strobe signal CAS.sub.L.
FIG. 4 is a timing chart showing the operation of the DRAM shown in FIG. 3 when the upper column address strobe signal CAS.sub.U and the lower column address strobe signal CAS.sub.L in phase are applied to the DRAM. As shown in the figure, with the upper column address strobe signal CAS.sub.U and the lower column address strobe signal CAS.sub.L being in phase, an output of the upper bit group BG.sub.U and an output of the lower group BG.sub.L collides with each other on data transmission bus 2.
A conventional approach for preventing the collision of data is to activate one of the upper column address strobe signal CAS.sub.U and the lower column address strobe signal CAS.sub.L and deactivate the other. For example in FIG. 5, only the upper column address strobe signal CAS.sub.U is activated. Only data from the upper bit group BG.sub.U is therefore output onto data transmission bus 2.
When connected to a data transmission bus having a small bit width, a conventional semiconductor memory device structured as described above can output only m-bit data, which is only the half of the output bit width n the semiconductor memory device actually has, and the data transmission rate is therefore low.